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functional block diagram 2.5v reference calibration memory and controller parallel interface/control register i/p mux charge redistribution dac sar + adc control t/h buf ain1 ain8 ref in / ref out c ref1 c ref2 cal dv dd dgnd clkin convst busy sleep av dd agnd db15 ?db0 rd cs wr w/b ad7859/ad7859l comp rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a 3 v to 5 v single supply, 200 ksps 8-channel, 12-bit sampling adcs ad7859/ad7859l features specified for v dd of 3 v to 5.5 v ad7859C200 ksps; ad7859lC100 ksps system and self-calibration low power normal operation ad7859: 15 mw (v dd = 3 v) ad7859l: 5.5 mw (v dd = 3 v) using automatic power-down after conversion (25 m w) ad7859: 1.3 mw (v dd = 3 v 10 ksps) ad7859l: 650 m w (v dd = 3 v 10 ksps) flexible parallel interface: 16-bit parallel/8-bit parallel 44-pin pqfp and plcc packages applications battery-powered systems (personal digital assistants, medical instruments, mobile communications) pen computers instrumentation and control systems high speed modems ? analog devices, inc., 1996 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 general description the ad7859/ad7859l are high speed, low power, 8-channel, 12-bit adcs which operate from a single 3 v or 5 v power supply, the ad7859 being optimized for speed and the ad7859l for low power. the adc contains self-calibration and system calibration options to ensure accurate operation over time and temperature and have a number of power-down options for low power applications. the ad7859 is capable of 200 khz throughput rate while the ad7859l is capable of 100 khz throughput rate. the input track-and-hold acquires a signal in 500 ns and features a pseudo- differential sampling scheme. the ad7859 and ad7859l input voltage range is 0 to v ref (unipolar) and Cv ref /2 to +v ref /2 about v ref /2 (bipolar) with both straight binary and 2s comple- ment output coding respectively. input signal range is to the supply and the part is capable of converting full-power signals to 100 khz. cmos construction ensures low power dissipation of typically 5.4 mw for normal operation and 3.6 m w in power-down mode. the part is available in 44-pin, plastic quad flatpack package (pqfp) and plastic lead chip carrier (plcc). see page 28 for data sheet index. product highlights 1. operation with either 3 v or 5 v power supplies. 2. flexible power management options including automatic power-down after conversion. 3. by using the power management options a superior power performance at slower throughput rates can be achieved. ad7859: 1 mw typ @ 10 ksps ad7859l: 1 mw typ @ 20 ksps 4. operates with reference voltages from 1.2 v to the supply. 5. analog input ranges from 0 v to v dd . 6. self and system calibration. 7. versatile parallel i/o port. 8. lower power version ad7859l.
parameter a version 1 b version 1 units test conditions/comments dynamic performance signal to noise + distortion ratio 3 70 71 db min typically snr is 72 db (snr) v in = 10 khz sine wave, f sample = 200 khz (for l version: f sample = 100 khz @ f clkin = 2 mhz) total harmonic distortion (thd) C78 C78 db max v in = 10 khz sine wave, f sample = 200 khz (for l version: f sample = 100 khz @ f clkin = 2 mhz) peak harmonic or spurious noise C78 C78 db max v in = 10 khz sine wave, f sample = 200 khz (for l version: f sample = 100 khz @ f clkin = 2 mhz) intermodulation distortion (imd) second order terms C78 C78 db typ fa = 9.983 khz, fb = 10.05 khz, f sample = 200 khz (for l version: f sample = 100 khz @ f clkin = 2 mhz) third order terms C78 C78 db typ fa = 9.983 khz, fb = 10.05 khz, f sample = 200 khz (for l version: f sample = 100 khz @ f clkin = 2 mhz) channel-to-channel isolation C80 C80 db typ v in = 25 khz dc accuracy resolution 12 12 bits integral nonlinearity 1 0.5 lsb max 5 v reference v dd = 5 v differential nonlinearity 1 1 lsb max guaranteed no missed codes to 12 bits unipolar offset error 5 5 lsb max 2 2 lsb typ unipolar offset error match 2(3) 2 lsb max positive full-scale error 5 5 lsb max 2 2 lsb typ negative full-scale error 2 2 lsb max full-scale error match 1 1 lsb max bipolar zero error 1 1 lsb typ bipolar zero error match 2 2 lsb typ analog input input voltage ranges 0 to v ref 0 to v ref volts i.e., ain(+) C ain(C) = 0 to v ref , ain(C) can be biased up but ai n(+) cannot go below ain(C) v ref /2 v ref /2 volts i.e., ain(+) C ain(C) = Cv ref /2 to +v ref /2, ain(C) should be biased to +v ref /2 and ain(+) can go below ain(C) but cannot go below 0 v leakage current 1 1 m a max input capacitance 20 20 pf typ reference input/output ref in input voltage range 2.3/v dd 2.3/v dd v min/max functional from 1.2 v input impedance 150 150 k w typ ref out output voltage 2.3/2.7 2.3/2.7 v min/max ref out tempco 20 20 ppm/ c typ logic inputs input high voltage, v inh 2.4 2.4 v min av dd = dv dd = 4.5 v to 5.5 v 2.1 2.1 v min av dd = dv dd = 3.0 v to 3.6 v cal pin 3 3 v min av dd = dv dd = 4.5 v to 5.5 v 2.4 2.4 v min av dd = dv dd = 3.0 v to 3.6 v input low voltage, v inl 0.8 0.8 v max av dd = dv dd = 4.5 v to 5.5 v 0.6 0.6 v max av dd = dv dd = 3.0 v to 3.6 v input current, i in 10 10 m a max typically 10 na, v in = 0 v or v dd input capacitance, c in 4 10 10 pf max logic outputs output high voltage, v oh 4 4 v min av dd = dv dd = 4.5 v to 5.5 v 2.4 2.4 v min av dd = dv dd = 3.0 v to 3.6 v output low voltage, v ol 0.4 0.4 v max i sink = 1.6 ma floating state leakage current 10 10 m a max floating-state output capacitance 4 10 10 pf max output coding straight (natural) binary unipolar input range 2s complement bipolar input range ad7859/ad7859lCspecifications 1, 2 (av dd = dv dd = +3.0 v to +5.5 v, ref in /ref out = 2.5 v external reference, f clkin = 4 mhz (for l version: 1.8 mhz (0 8 c to +70 8 c) and 1 mhz (C40 8 c to +85 8 c)); f sample = 200 khz (ad7859) 100 khz (ad7859l); sleep = logic high; t a = t min to t max , unless otherwise noted.) specifications in () apply to the ad7859l. C2C rev. a
rev. a C3C parameter a version 1 b version 1 units test conditions/comments conversion rate t clkin 18 conversion time 4.5 (10) 4.5 m s max (l versions only, 0 c to +70 c, 1.8 mhz clkin) track/hold acquisition time 0.5 (1) 0.5 m s min (l versions only, C40 c to +85 c, 1.8 mhz clkin) power requirements av dd, dv dd +3.0/+5.5 +3.0/+5.5 v min/max i dd normal mode 5 5.5 (1.95) 5.5 ma max av dd = dv dd = 4.5 v to 5.5 v. typically 4.5 ma 5.5 (1.95) 5.5 ma max av dd = dv dd = 3.0 v to 3.6 v. typically 4.0 ma sleep mode 6 with external clock on 10 10 m a typ full power-down. power management bits in co ntrol register set as pmgt1 = 1, pmgt0 = 0. 400 400 m a typ partial power-down. power management bits in control register set as pmgt1 = 1, pmgt0 = 1. with external clock off 5 5 m a max typically 1 m a. full power-down. power manage ment bits in control register set as pmgt1 = 1, pmgt0 = 0. 200 200 m a typ partial power-down. power management bits in control register set as pmgt1 = 1, pmgt0 = 1. normal mode power dissipation 30 (10) 30 (10) mw max v dd = 5.5 v: typically 25 mw (8); sleep = v dd 20 (6.5) 20 (6.5) mw max v dd = 3.6 v: typically 15 mw (5.4); sleep = v dd sleep mode power dissipation with external clock on 55 55 m w typ v dd = 5.5 v; sleep = 0 v 36 36 m w typ v dd = 3.6 v; sleep = 0 v with external clock off 27.5 27.5 m w max v dd = 5.5 v: typically 5.5 m w; sleep = 0 v 18 18 m w max v dd = 3.6 v: typically 3.6 m w; sleep = 0 v system calibration offset calibration span 7 +0.05 v ref /C0.05 v ref v max/min allowable offset voltage span for calibration gain calibration span 7 +1.025 v ref /C0.975 v ref v max/min allowable full-scale voltage span for calibration notes 1 temperature range as follows: a, b versions, C40 c to +85 c. 2 specifications apply after calibration. 3 snr calculation includes distortion and noise components. 4 not production tested, guaranteed by characterization at initial product release. 5 all digital inputs @ dgnd except for convst , sleep, cal, and sync @ dv dd . no load on the digital outputs. analog inputs @ agnd. 6 clkin @ dgnd when external clock off. all digital inputs @ dgnd except for convst , sleep , cal , and sync @ dv dd . no load on the digital outputs. analog inputs @ agnd. 7 the offset and gain calibration spans are defined as the range of offset and gain errors that the ad7859/ad7859l can calibrate. note also that these are voltage spans and are not absolute voltages (i.e., the allowable system offset voltage presented at ain(+) for the system offset error to be adjusted out will be ain(C) 0.05 v ref , and the allowable system full-scale voltage applied between ain(+) and ain(C) for the system full-scale voltage error to be adjusted out will be v ref 0.025 v ref ). this is explained in more detail in the calibration section of the data sheet. specifications subject to change without notice. ad7859/ad7859l
ad7859/ad7859l rev. a C4C limit at t min , t max (a, b versions) parameter 5 v 3 v units description f clkin 2 500 500 khz min master clock frequency 4 4 mhz max 1.8 1.8 mhz max l version t 1 3 100 100 ns min convst pulse width t 2 50 90 ns max convst to busy - propagation delay t convert 4.5 4.5 m s max conversion time = 18 t clkin 10 10 m s max l version 1.8 mhz clkin. conversion time = 18 t clkin t 3 15 15 ns min hben to rd setup time t 4 5 5 ns min hben to rd hold time t 5 0 0 ns min cs to rd to setup time t 6 0 0 ns min cs to rd hold time t 7 55 55 ns min rd pulse width t 8 4 50 50 ns max data access time after rd t 9 5 5 5 ns min bus relinquish time after rd 40 40 ns max bus relinquish time after rd t 10 60 70 ns min minimum time between reads t 11 0 0 ns min hben to wr setup time t 12 5 5 ns max hben to wr hold time t 13 0 0 ns min cs to wr setup time t 14 0 0 ns max cs to wr hold time t 15 55 70 ns min wr pulse width t 16 10 10 ns min data setup time before wr t 17 5 5 ns min data hold time after wr t 18 4 1/2 t clkin 1/2 t clkin ns min new data valid before falling edge of busy t 19 2.5 t clkin 2.5 t clkin ns max cs - to busy - in calibration sequence t cal 6 31.25 31.25 ms typ full self-calibration time, master clock dependent (125013 t clkin ) t cal1 6 27.78 27.78 ms typ internal dac plus system full-scale cal time, master clock dependent (111124 t clkin ) t cal2 6 3.47 3.47 ms typ system offset calibration time, master clock dependent (13889 t clkin ) notes 1 sample tested at +25 c to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. 2 mark/space ratio for the master clock input is 40/60 to 60/40. 3 the convst pulse width will here only apply for normal operation. when the part is in power-down mode, a different convst pulse width will apply (see power- down section). 4 measured with the load circuit of figure 1 and defined as the time required for the output to cross 0.8 v or 2.4 v. 5 t 9 is derived form the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 1. the measured number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the time, t 9 , quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 6 the typical time specified for the calibration times is for a master clock of 4 mhz. for the l version the calibration times will be longer than those quoted here due to the 1.8 mhz master clock. specifications subject to change without notice. timing specifications 1 (av dd = dv dd = +3.0 v to +5.5 v; f clkin = 4 mhz for ad7859 and 1.8 mhz for ad7859l; t a = t min to t max , unless otherwise noted)
ad7859/ad7859l rev. a C5C absolute maximum ratings 1 (t a = +25 c unless otherwise noted) av dd to agnd . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v dv dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v av dd to dv dd . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +0.3 v analog input voltage to agnd . . . . C0.3 v to av dd + 0.3 v digital input voltage to dgnd . . . . C0.3 v to dv dd + 0.3 v digital output voltage to dgnd . . . C0.3 v to dv dd + 0.3 v ref in /ref out to agnd . . . . . . . . . C0.3 v to av dd + 0.3 v input current to any pin except supplies 2 . . . . . . . . 10 ma operating temperature range commercial (a, b versions) . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150 c pqfp package, power dissipation . . . . . . . . . . . . . . 450 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 95 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220 c plcc package, power dissipation . . . . . . . . . . . . . . 500 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . . . 55 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220 c esd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1500 kv notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latchup. to output pin 50pf 1.6ma i ol 200? i oh +2.1v figure 1. load circuit for digital output timing specifications ordering guide linearity power error dissipation package model (lsb) 1 (mw) option 2 ad7859ap 1 15 p-44a ad7859as 1 15 s-44 ad7859bs 1/2 15 s-44 ad7859las 3 1 5.5 s-44 eval-ad7859cb 4 eval-control board 5 notes 1 linearity error refers to the integral linearity error. 2 p = plcc; s = pqfp. 3 l signifies the low power version. 4 this can be used as a stand-alone evaluation board or in conjunction with the eval-control board for evaluation/demonstration purposes. 5 this board is a complete unit allowing a pc to control and communicate with all analog devices, inc. evaluation boards ending in the cb designators. for more information on analog devices products and evaluation boards, visit our world wide web home page at http://www.analog.com. pinout for plcc 18 19 20 21 22 23 24 25 26 27 28 2144 3456 42 41 40 43 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 nc w/b ref in /ref out av dd c ref1 ain0 c ref2 agnd ain1 ain2 ain3 dv dd dgnd db5 db6 db7 db8/hben db9 db10 db11 nc db4 ad7859 (not to scale) top view convst nc db14 clkin busy db12 db15 db13 wr rd cs nc db1 db2 db3 ain4 ain5 ain6 ain7 cal sleep db0 pinout for pqfp 6 7 1 2 3 4 5 8 9 10 11 23 24 25 26 27 28 29 30 31 32 33 22 21 20 19 18 17 16 15 14 13 12 ad7859 top view (not to scale) pin no. 1 identifier nc w/b ref in /ref out av dd c ref1 ain0 c ref2 agnd ain1 ain2 ain3 dv dd dgnd db5 db6 db7 db8/hben db9 db10 db11 nc db4 convst nc db14 clkin busy db12 db15 db13 wr rd cs nc db1 db2 db3 ain4 ain5 ain6 ain7 cal sleep db0 34 35 36 37 38 39 40 41 42 43 44
ad7859/ad7859l rev. a C6C total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the ad7859/ad7859l, it is defined as: thd ( db ) = 20 log ( v 2 2 + v 3 2 + v 4 2 + v 5 2 + v 6 2 ) v 1 where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is deter- mined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation distortion terms are those for which neither m nor n are equal to zero. for example, the second order terms include (fa + fb) and (fa C fb), while the third order terms include (2fa + fb), (2fa C fb), (fa + 2fb) and (fa C 2fb). testing is performed using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second order terms are usually distanced in fre- quency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. as a result, the second and third order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dbs. terminology integral nonlinearity this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the end- points of the transfer function are zero scale, a point 1/2 lsb below the first code transition, and full scale, a point 1/2 lsb above the last code transition. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. unipolar offset error this is the deviation of the first code transition (00 . . . 000 to 00 . . . 001) from the ideal ain(+) voltage (ain(C) + 1/2 lsb) when operating in the unipolar mode. positive full-scale error this applies to the unipolar and bipolar modes and is the devia- tion of the last code transition from the ideal ain(+) voltage (ain(C) + full scale C 1.5 lsb) after the offset error has been adjusted out. negative full-scale error this applies to the bipolar mode only and is the deviation of the first code transition (10 . . . 000 to 10 . . . 001) from the ideal ain(+) voltage (ain(C) C v ref /2 + 0.5 lsb). bipolar zero error this is the deviation of the midscale transition (all 0s to all 1s) from the ideal ain(+) voltage (ain(C) C 1/2 lsb). track/hold acquisition time the track/hold amplifier returns into track mode and the end of conversion. track/hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within 1/2 lsb, after the end of conversion. signal to (noise + distortion) ratio this is the measured ratio of signal to (noise + distortion) at the output of the a/d converter. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental sig- nals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantiza- tion noise. the theoretical signal to (noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by: signal to (noise + distortion) = ( 6.02 n + 1.76 )db thus for a 12-bit converter, this is 74 db.
ad7859/ad7859l rev. a C7C pin function description mnemonic description convst convert start. logic input. a low to high transition on this input puts the track/hold into its hold mode and starts conversion. when this input is not used, it should be tied to dv dd . rd read input. active low logic input. used in conjunction with cs to read from internal registers. wr write input. active low logic input. used in conjunction with cs to write to internal registers. cs chip select input. active low logic input. the device is selected when this input is active. ref in / reference input/output. this pin is connected to the internal reference through a series resistor and is the ref out reference source for the analog-to-digital converter. the nominal reference voltage is 2.5 v and this appears at the pin. this pin can be overdriven by an external reference or can be taken as high as av dd . when this pin is tied to av dd , then the c ref1 pin should also be tied to av dd . av dd analog supply voltage, +3.0 v to +5.5 v. agnd analog ground. ground reference for track/hold, reference and dac. dv dd digital supply voltage, +3.0 v to +5.5 v. dgnd digital ground. ground reference point for digital circuitry. c ref1 reference capacitor (0.1 m f multilayer ceramic). this external capacitor is used as a charge source for the inter- nal dac. the capacitor should be tied between the pin and agnd. c ref2 reference capacitor (0.01 m f ceramic disc). this external capacitor is used in conjunction with the on-chip refer- ence. the capacitor should be tied between the pin and agnd. ain1Cain8 analog inputs. eight analog inputs which can be used as eight single ended inputs (referenced to agnd) or four pseudo differential inputs. channel configuration is selected by writing to the control register. none of the inputs can go below agnd or above av dd at any time. see table iii for channel selection. w/ b word/byte input. when this input is at a logic 1, data is transferred to and from the ad7859/ad7859l in 16-bit words on pins db0 to db15. when this pin is at a logic 0, byte transfer mode is enabled. data is transferred on pins db0 to db7 and pin db8/hben assumes its hben functionality. db0Cdb7 data bits 0 to 7. three state data i/o pins that are controlled by cs , rd and wr . data output is straight binary (unipolar mode) or twos complement (bipolar mode). db8/hben data bit 8/high byte enable. when w/ b is high, this pin acts as data bit 7, a three state data i/o pin that is con- trolled by cs , rd and wr . when w/ b is low, this pin acts as the high byte enable pin. when hben is low, then the low byte of data being written to or read from the ad7859/ad7859l is on db0 to db7. when hben is high, then the high byte of data being written to or read from the ad7859/ad7859l is on db0 to db7. db9Cdb15 data bits 9 to 15. three state data i/o pins that are controlled by cs , rd and wr . data output is straight bi- nary (unipolar mode) or twos complement (bipolar mode). clkin master clock signal for the device (4 mhz for ad7859, 1.8 mhz for ad7859l). sets the conversion and calibra- tion times. cal calibration input. a logic 0 in this pin resets all logic. a rising edge on this pin initiates a calibration. this input overrides all other internal operations. busy busy output. the busy output is triggered high when a conversion or a calibration is initiated, and remains high until the conversion or calibration is completed. sleep sleep input. this pin is used in conjunction with the pgmt0 and pgmt1 bits in the control register to deter- mine the power-down mode. please see the power-down options section for details. nc no connect pins. these pins should be left unconnected.
ad7859/ad7859l rev. a C8C ad7859/ad7859l on-chip registers the ad7859/ad7859l powers up with a set of default conditions. the only writing that is required is to select the channel configu- ration. without performing any other write operations, the ad7859/ad7859l still retains the flexibility for performing a full power- down and a full self-calibration. extra features and flexibility such as performing different power-down options, different types of calibrations, including system cali- bration, and software conversion start can be selected by writing to the part. the ad7859/ad7859l contains a control register, adc output data register, status register, test register and 10 cali- bration registers . the control register is write-only, the adc output data register and the status register are read-only, and the test and calibration registers are both read/write registers. the test register is used for testing the part and should not be written to. addressing the on-chip registers writing when writing to the ad7859/ad7859l, a 16-bit word of data must be transferred. the 16 bits of data is written as either a 16-bit word, or as two 8-bit bytes, depending on the logic level at the w/ b pin. when w/ b is high, the 16 bits are transferred on db0 to db15, where db0 is the lsb and db15 is the msb of the write. when w/ b is low, db8/hben assumes its hben functionality and data is transferred in two 8-bit bytes on pins db0 to db7, pin db0 being the lsb of each transfer and pin db7 being the msb. when writing to the ad7859/ad7859l in byte mode, the low byte must be written first followed by the high byte. the two msbs of the complete 16-bit word, addr1 and addr0, are decoded to determine which register is addressed, and the 14 lsbs are writ- ten to the addressed register. table i shows the decoding of the address bits, while figure 2 shows the overall write register hierarchy. table i. write register addressing addr1 addr0 comment 0 0 this combination does not address any register. 0 1 this combination addresses the test register . the 14 lsbs of data are written to the test register. 1 0 this combination addresses the calibration registers . the 14 lsbs of data are written to the selected calibration register. 1 1 this combination addresses the control register . the 14 lsbs of data are written to the control register. reading to read from the various registers the user must first write to bits 6 and 7 in the control register, rdslt0 and rdslt1. these bits are decoded to determine which register is addressed during a read operation. table ii shows the decoding of the read address bits while figure 3 shows the overall read register hierarchy. the power-up status of these bits is 00 so that the default read will be from the adc output data register. as with writing to the ad7859/ad7859l either word or byte mode can be used. when reading from the calibration registers in byte mode, the low byte must be read first. once the read selection bits are set in the control register all subsequent read operations that follow are from the selected register un- til the read selection bits are changed in the control register. table ii. read register addressing rdslt1 rdslt0 comment 0 0 all successive read operations are from the adc output data register . this is the default power- up setting. there is always four leading zeros when reading from the adc output data register. 0 1 all successive read operations are from the test register . 1 0 all successive read operations are from the calibration registers . 1 1 all successive read operations are from the status register . test register calibration registers status register gain (1) offset (1) dac (8) gain (1) offset (1) offset (1) gain (1) 01 10 11 00 01 10 11 calslt1, calslt0 decode adc output data register 00 rdslt1, rdslt0 decode figure 3. read register hierarchy/address decoding addr1, addr0 decode test register control register gain (1) offset (1) dac (8) gain (1) offset (1) offset (1) gain (1) 01 10 11 00 01 10 11 calslt1, calslt0 decode calibration registers figure 2. write register hierarchy/address decoding
ad7859/ad7859l rev. a C9C control register the arrangement of the control register is shown below. the control register is a write only register and contains 14 bits of data. the control register is selected by putting two 1s in addr1 and addr0. the function of the bits in the control register is described below. the power-up status of all bits is 0. msb sgl/ diff chslt2 chslt1 chslt0 pmgt1 pmgt0 rdslt1 rdslt0 amode convst calmd calslt1 calslt0 stcal lsb control register bit function description bit mnemonic comment 13 sgl/ diff a 0 in this bit position configures the input channels for pseudo-differential mode. a 1 in this bit posi- tion configures the input channels in single ended mode. please see table iii for channel selection. 12 chslt2 these three bits are used to select the analog input on which the conversion is performed. the analog 11 chslt1 inputs can be configured as eight single-ended channels or four pseudo-differential channels. the 10 chslt0 default selection is ain1 for the positive input and ain2 for the negative input. please see table iii for channel selection information. 9 pmgt1 power management bits. these two bits are used with the sleep pin for putting the part into various 8 pmgt0 power-down modes (see power-down section for more details). 7 rdslt1 theses two bits determine which register is addressed for the read operations. please see table ii. 6 rdslt0 5 amode analog mode bit. this bit has two different functions, depending on the status of the sgl/ diff bit. when sgl/ diff is 0, amode selects between unipolar and bipolar analog input ranges. a logic 0 in this bit position selects the unipolar range, 0 to v ref (i.e., ain(+) C ain(C) = 0 to v ref ). a logic 1 in this bit position selects the bipolar range Cv ref /2 to +v ref /2 (i.e., ain(+) C ain(C) = Cv ref /2 to +v ref /2). in this case ain(C) needs to be tied to at least +v ref /2 to allow ain(+) to have a full input swing from 0 v to +v ref . when sgl/ diff is 1, amode selects the source for the ain(C) channel of the sample and hold cir- cuitry. if amode is a 0, agnd is selected. if amode is a 1, then ain8 is selected. please see table iii for more information. 4 convst conversion start bit. a logic 1 in this bit position starts a single conversion, and this bit is automatically reset to 0 at the end of conversion. this bit may also be used in conjunction with system calibration (see calibration section on page 21). 3 calmd calibration mode bit. a 0 here selects self-calibration and a 1 selects a system calibration (see table iv). 2 calslt1 calibration selection bits 1 and 0. these bits have two functions, depending on the stcal bit. 1 calslt0 with the stcal bit set to 1, the calslt1 and calslt0 bits, along with the calmd bit, deter- mine the type of calibration performed by the part (see table iv). with the stcal bit set to 0, the calslt1 and calslt0 bits are decoded to address the calibration register for read/write of calibration coefficients (see table v for more details). 0 stcal start calibration bit. when stcal is set to a 1, a calibration is performed, as determined by the calmd, calslt1 and calslt0 bits. please see table iv. when stcal is set to a zero, no cali- bration is performed.
ad7859/ad7859l rev. a C10C table iv. calibration selection calmd calslt1 calslt0 calibration type 00 0 a full internal calibration is initiated. first the internal dac is calibrated, then the internal gain error and finally the internal offset error are removed. this is the default setting. 0 0 1 first the internal gain error is removed, then the internal offset error is removed. 0 1 0 the internal offset error only is calibrated out. 0 1 1 the internal gain error only is calibrated out. 10 0 a full system calibration is initiated. first the internal dac is calibrated, followed by the system gain error calibration, and finally the system offset error calibration. 1 0 1 first the system gain error is calibrated out, followed by the system offset error . 1 1 0 the system offset error only is removed. 1 1 1 the system gain error only is removed. table iiia. channel selection for ad7859/ad7859l differential sampling (sgl/diff = 0) amode chslt ain(+)*ain(C)* bipolar or 2 1 0 unipolar 0 0 0 0 ain1 ain2 unipolar 0 0 0 1 ain3 ain4 unipolar 0 0 1 0 ain5 ain6 unipolar 0 0 1 1 ain7 ain8 unipolar 0 1 x x x x not used 1 0 0 0 ain1 ain2 bipolar 1 0 0 1 ain3 ain4 bipolar 1 0 1 0 ain5 ain6 bipolar 1 0 1 1 ain7 ain8 bipolar 1 1 x x x x not used *ain(+) refers to the positive input seen by the ad7859/ad7859l sample-and- hold circuitry. ain(C) refers to the negative input seen by the ad7859/ad7859l sample-and- hold circuitry. table iiib. channel selection for ad7859/ad7859l single-ended sampling (sgl/diff = 1) amode chslt ain(+)*ain(C)* bipolar or 2 1 0 unipolar 0 0 0 0 ain1 agnd unipolar 0 0 0 1 ain3 agnd unipolar 0 0 1 0 ain5 agnd unipolar 0 0 1 1 ain7 agnd unipolar 0 1 0 0 ain2 agnd unipolar 0 1 0 1 ain4 agnd unipolar 0 1 1 0 ain6 agnd unipolar 0 1 1 1 ain8 agnd unipolar 1 0 0 0 ain1 ain8 unipolar 1 0 0 1 ain3 ain8 unipolar 1 0 1 0 ain5 ain8 unipolar 1 0 1 1 ain7 ain8 unipolar 1 1 0 0 ain2 ain8 unipolar 1 1 0 1 ain4 ain8 unipolar 1 1 1 0 ain6 ain8 unipolar 1 1 1 1 ain8 ain8 unipolar
ad7859/ad7859l rev. a C11C status register the arrangement of the status register is shown below. the status register is a read-only register and contains 16 bits of data. the status register is selected by first writing to the control register and putting two 1s in rdslt1 and rdslt0. the function of the bits in the status register are described below. the power-up status of all bits is 0. write to control register setting rdslt0 = rdslt1 = 1 read status register start figure 4. flowchart for reading the status register msb zero zero sgl/ diff chslt2 chslt1 chslt0 pmgt1 pmgt0 one one amode busy calmd calslt1 calslt0 stcal lsb status register bit function description bit mnemonic comment 15 zero these two bits are always 0. 14 zero 13 sgl/ diff single/differential bit. 12 chslt2 channel selection bits. these bits, in conjunction with the sgl/ diff bit, determine which channel has 11 chslt1 been selected for conversion. please refer to table iiia and table iiib. 10 chslt0 9 pmgt1 power management bits. these bits along with the sleep pin indicate if the part is in a power-down 8 pmgt0 mode or not. see table vi in power-down section for description. 7 one both these bits are always 1. 6 one 5 amode analog mode bit. this bit is used along with sgl/diff and chslt2 C chslt0 to determine the ain(+) and ain(C) inputs to the track and hold circuitry and the analog conversion mode (unipolar or bi- polar). please see table iii for details. 4 busy conversion/calibration busy bit. when this bit is a 1, there is a conversion or a calibration in progress. when this bit is a zero, there is no conversion or calibration in progress. 3 calmd calibration mode bit. a 0 in this bit indicates a self-calibration is selected, and a 1 in this bit indicates a system calibration is selected (see table iv). 2 calslt1 calibration selection bits. the calslt1 and calslt0 bits indicate which of the calibration 1 calslt0 registers are addressed for reading and writing (see section on the calibration registers for more details). 0 stcal start calibration bit. the stcal bit is a 1 if a calibration is in progress and a 0 if there is no calibration in progress.
ad7859/ad7859l rev. a C12C calibration registers the ad7859/ad7859l has 10 calibration registers in all, 8 for the dac, 1 for offset and 1 for gain. data can be written to or read from all 10 calibration registers. in self and system calibration, the part automatically modifies the calibration registers; only if the user needs to modify the calibration registers should an attempt be made to read from and write to the calibration registers. addressing the calibration registers the calibration selection bits in the control register calslt1 and calslt0 determine which of the calibration registers are ad- dressed (see table v). the addressing applies to both the read and write operations for the calibration registers. the user should not attempt to read from and write to the calibration registers at the same time. table v. calibration register addressing calslt1 calslt0 comment 0 0 this combination addresses the gain (1) , offset (1) and dac registers (8) . ten registers in total. 0 1 this combination addresses the gain (1) and offset (1) registers. two registers in total. 1 0 this combination addresses the offset register . one register in total. 1 1 this combination addresses the gain register . one register in total. writing to/reading from the calibration registers when writing to the calibration registers a write to the control register is required to set the calslt0 and calslt1 bits. when reading from the calibration registers a write to the con- trol register is required to set the calslt0 and calslt1 bits and also to set the rdslt1 and rdslt0 bits to 10 (this ad- dresses the calibration registers for reading). the calibration register pointer is reset on writing to the control register setting the calslt1 and calslt0 bits, or upon completion of all the calibration register write/read operations. when reset it points to the first calibration register in the selected write/read sequence. the calibration register pointer points to the gain calibration register upon reset in all but one case, this case being where the offset calibration register is selected on its own (calslt1 = 1, calslt0 = 0). where more than one cali- bration register is being accessed, the calibration register pointer is automatically incremented after each full calibration register write/read operation. the calibration register address pointer is incremented after the high byte read or write operation in byte mode. therefore when reading (in byte mode) from the calibra- tion registers, the low byte must always be read first, i.e., hben = logic zero. the order in which the 10 calibration registers are arranged is shown in figure 5. read/write operations may be aborted at any time before all the calibration registers have been accessed, and the next control register write operation resets the calibration register pointer. the flowchart in figure 6 shows the sequence for writing to the calibration registers. figure 7 shows the sequence for reading from the calibration registers. cal register address pointer calibration registers gain register offset register dac 1st msb register dac 8th msb register (1) (2) (3) (10) calibration register address pointer position is determined by the number of calibration registers addressed and the number of read/write operations. figure 5. calibration register arrangement when reading from the calibration registers there is always two leading zeros for each of the registers. start write to cal register (addr1 = 1, addr0 = 0) finished last register write operation or abort ? yes no cal register pointer is automatically reset write to control register setting stcal = 0 and calslt1, calslt0 = 00, 01, 10, 11 cal register pointer is automatically incremented figure 6. flowchart for writing to the calibration registers
ad7859/ad7859l rev. a C13C finished last register write operation or abort ? yes no cal register pointer is automatically incremented read cal register cal register pointer is automatically reset write to control register setting stcal = 0, rdslt1 = 1, rdslt0 = 0, and calslt1, calslt0 = 00, 01, 10, 11 start figure 7. flowchart for reading from the calibration registers adjusting the offset calibration register the offset calibration register contains 16 bits. the two msbs are zero and the 14 lsbs contain offset data. by changing the contents of the offset register, different amounts of offset on the analog input signal can be compensated for. decreasing the number in the offset calibration register compensates for nega- tive offset on the analog input signal, and increasing the number in the offset calibration register compensates for positive offset on the analog input signal. the default value of the offset cali- bration register is 0010 0000 0000 0000 approximately. this is not the exact value, but the value in the offset register should be close to this value. each of the 14 data bits in the offset register is binary weighted; the msb has a weighting of 5% of the refer- ence voltage, the msb-1 has a weighting of 2.5%, the msb-2 has a weighting of 1.25%, and so on down to the lsb which has a weighting of 0.0006%. this gives a resolution of 0.0006% of v ref approximately. the resolution can also be expressed as (0.05 v ref )/2 13 volts. this equals 0.015 mv, with a 2.5 v reference. the maximum offset that can be compensated for is 5% of the reference voltage, which equates to 125 mv with a 2.5 v reference and 250 mv with a 5 v reference. q. if a +20 mv offset is present in the analog input signal and the reference voltage is 2.5 v, what code needs to be written to the offset register to compensate for the offset ? a. 2.5 v reference implies that the resolution in the offset reg- ister is 5% 2.5 v/2 13 = 0.015 mv. +20 mv/0.015 mv = 1310.72; rounding to the nearest number gives 1311. in binary terms this is 00 0101 0001 1111, therefore increase the offset register by 00 0101 0001 1111. this method of compensating for offset in the analog input sig- nal allows for fine tuning the offset compensation. if the offset on the analog input signal is known, there is no need to apply the offset voltage to the analog input pins and do a system cali- bration. the offset compensation can take place in software. adjusting the gain calibration register the gain calibration register contains 16 bits. the two msbs are zero and the 14 lsbs contain gain data. as in the offset cali- brating register the data bits in the gain calibration register are binary weighted, with the msb having a weighting of 2.5% of the reference voltage. the gain register value is effectively multi- plied by the analog input to scale the conversion result over the full range. increasing the gain register compensates for a smaller analog input range and decreasing the gain register com- pensates for a larger input range. the maximum analog input range that the gain register can compensate for is 1.025 times the reference voltage, and the minimum input range is 0.975 times the reference voltage.
ad7859/ad7859l rev. a C14C and 1.5 clkin periods are allowed for the acquisition time. with a 1.8 mhz clock, this gives a full cycle time of 10 m s, which equates to a throughput rate of 100 ksps. when using the software conversion start for maximum throughput, the user must ensure the control register write op- eration extends beyond the falling edge of busy. the falling edge of busy resets the convst bit to 0 and allows it to be reprogrammed to 1 to start the next conversion. typical connection diagram figure 8 shows a typical connection diagram for the ad7859/ ad7859l. the agnd and the dgnd pins are connected together at the device for good noise suppression. the first convst applied after power-up starts a self-calibration sequence. this is explained in the calibration section of this data sheet. note that after power is applied to av dd and dv dd and the convst signal is applied, the part requires (70 ms + 1/ sample rate) for the internal reference to settle and for the self- calibration on power-up to be completed. av dd dv dd ain(+) ain(? c ref1 c ref2 sleep db15 db0 convst agnd dgnd clkin ref in /ref out ad7859/ ad7859l analog supply +3v to +5v 0.1? 0.1? 10? 0.1? 0.01? conversion start signal 0.1nf external ref 0.1? internal ref cal 0v to 2.5v input 4mhz/1.8mhz oscillator optional external reference cs rd wr w/b busy dv dd ?/? ad780/ ref192 figure 8. typical circuit for applications where power consumption is a major concern, the power-down options can be exercised by writing to the part and using the sleep pin. see the power-down section for more details on low power applications. circuit information the ad7859/ad7859l is a fast, 8-channel, 12-bit, single sup- ply a/d converter. the part requires an external 4 mhz/1.8 mhz master clock (clkin), two c ref capacitors, a convst signal to start conversion and power supply decoupling capaci- tors. the part provides the user with track/hold, on-chip refer- ence, calibration features, a/d converter and parallel interface logic functions on a single chip. the a/d converter section of the ad7859/ad7859l consists of a conventional successive-ap- proximation converter based around a capacitor dac. the ad7859/ad7859l accepts an analog input range of 0 to +v ref. v ref can be tied to v dd . the reference input to the part con- nected via a 150 k w resistor to the internal 2.5 v reference and to the on-chip buffer. a major advantage of the ad7859/ad7859l is that a conver- sion can be initiated in software, as well as by applying a signal to the convst pin. the part is available in a 44-pin plcc or a 44-pin pqfp package, and this offers the user considerable spacing saving advantages over alternative solutions. the ad7859l version typically consumes only 5.5 mw making it ideal for battery-powered applications. converter details the master clock for the part is applied to the clkin pin. conversion is initiated on the ad7859/ad7859l by pulsing the convst input or by writing to the control register and setting the convst bit to 1. on the rising edge of convst (or at the end of the control register write operation), the on-chip track/hold goes from track to hold mode. the falling edge of the clkin signal which follows the rising edge of convst ini- tiates the conversion, provided the rising edge of convst (or wr when converting via the control register) occurs typically at least 10 ns before this clkin edge. the conversion takes 16.5 clkin periods from this clkin falling edge. if the 10 ns set- up time is not met, the conversion takes 17.5 clkin periods. the time required by the ad7859/ad7859l to acquire a signal depends upon the source resistance connected to the ain(+) in- put. please refer to the acquisition time section for more details. when a conversion is completed, the busy output goes low, and the result of the conversion can be read by accessing the data through the data bus. to obtain optimum performance from the part, read or write operations should not occur during the conversion or less than 200 ns prior to the next convst rising edge. reading/writing during conversion typically de- grades the signal-to-(noise + distortion) by less than 0.5 dbs. the ad7859 can operate at throughput rates of over 200 ksps (up to 100 ksps for the ad7859l). with the ad7859l, 100 ksps throughput can be obtained as follows: the clkin and convst signals are arranged to give a conversion time of 16.5 clkin periods as described above
ad7859/ad7859l rev. a C15C dc/ac applications for dc applications, high source impedances are acceptable, provided there is enough acquisition time between conversions to charge the 20 pf capacitor. for example with r in = 5 k w , the required acquisition time is 922 ns. for ac applications, removing high frequency components greater than the nyquist frequency from the analog input signal is recommended by use of a low- pass filter on the ain(+) pin, as shown in figure 11. in applications where harmonic distor- tion and signal to noise ratio are critical, the analog input should be driven from a low impedance source. large source imped- ances significantly affect the ac performance of the adc. they may require the use of an input buffer amplifier. the choice of the amplifier is a function of the particular application. the maximum source impedance depends on the amount of to- tal harmonic distortion (thd) that can be tolerated. the thd increases as the source impedance increases. figure 10 shows a graph of the total harmonic distortion vs. analog input signal frequency for different source impedances. with the setup as in figure 11, the thd is at the C90 db level. with a source im- pedance of 1 k w and no capacitor on the ain(+) pin, the thd increases with frequency. thd ?db input frequency ?khz ?2 ?6 ?2 0 100 20 40 60 80 ?8 ?0 ?4 thd vs. frequency for different source impedances r in = 1k w r in = 50k w, 10nf as in figure 13 figure 10. thd vs. analog input frequency in a single supply application (both 3 v and 5 v), the v+ and vC of the op amp can be taken directly from the supplies to the ad7859/ad7859l which eliminates the need for extra external power supplies. when operating with rail-to-rail inputs and out- puts at frequencies greater than 10 khz, care must be taken in selecting the particular op amp for the application. in particular, for single supply applications the input amplifiers should be connected in a gain of C1 arrangement to get the optimum per- formance. figure 11 shows the arrangement for a single supply application with a 50 w and 10 nf low-pass filter (cutoff fre- quency 320 khz) on the ain(+) pin. note that the 10 nf is a capacitor with good linearity to ensure good ac performance. recommended single supply op amps are the ad820 and the ad820-3v. analog input the equivalent analog input circuit is shown in f igure 9. ain(+) is the channel connected to the positive input of the track/hold circuitry and ain(C) is the channel connected to the negative input. please refer to table iiia and table iiib for channel configuration. during the acquisition interval the switches are both in the track position and the ain(+) charges the 20 pf capacitor through the 125 w resistance. the rising edge of convst switches sw1 and sw2 go into the hold position retaining charge on the 20 pf capacitor as a sample of the signal on ain(+). the ain(C) is connected to the 20 pf capacitor, and this unbalances the voltage at node a at the input of the comparator. the capacitor dac adjusts during the remainder of the conversion cycle to restore the voltage at node a to the correct value. this action transfers a charge, representing the analog input signal, to the capacitor dac which in turn forms a digital representation of the analog input signal. the voltage on the ain(C) pin directly influences the charge transferred to the capacitor dac at the hold instant. if this voltage changes during the conversion period, the dac representation of the analog input voltage is altered. therefore it is most important that the voltage on the ain(C) pin remains constant during the conversion period. furthermore, it is recommended that the ain(C) pin is always connected to agnd or to a fixed dc voltage. capacitor dac comparator hold track sw2 node a 20pf sw1 track hold 125w 125w ain(+) ain(? agnd figure 9. analog input equivalent circuit acquisition time the track-and-hold amplifier enters its tracking mode on the falling edge of the busy signal. the time required for the track-and-hold amplifier to acquire an input signal will depend on how quickly the 20 pf input capacitance is charged. there is a minimum acquisition time of 400 ns. this includes the time required to change channels. for large source impedances, >2 k w , the acquisition time is calculated using the formula: t acq = 9 (r in + 125 w ) 20 pf where r in is the source impedance of the input signal, and 125 w , 20 pf is the input r, c.
ad7859/ad7859l rev. a C16C transfer functions for the unipolar range the designed code transitions occur mid- way between successive integer lsb values (i.e., 1/2 lsb, 3/2 lsbs, 5/2 lsbs . . . fs C3/2 lsbs). the output coding is straight binary for the unipolar range with 1 lsb = fs/4096 = 3.3 v/4096 = 0.8 mv when v ref = 3.3 v. figure 12 shows the unipolar analog input configuration. the ideal input/output transfer characteristic for the unipolar range is shown in figure 14. 1lsb = fs 4096 output code 111...111 111...110 111...101 111...100 000...011 000...010 000...001 000...000 0v 1lsb +fs ?lsb v in = ( ain(+) ?ain(? ) , input voltage figure 14. ad7859/ad7859l unipolar transfer characteristic figure 13 shows the ad7859/ad7859ls v ref /2 bipolar ana- log input configuration. ain(+) cannot go below 0 ,v so for the full bipolar range, ain(C) should be biased to at least +v ref /2. once again the designed code transitions occur mid- way between successive integer lsb values. the output coding is 2s complement with 1 lsb = 4096 = 3.3 v/4096 = 0.8 mv . the ideal input/output transfer characteristic is shown in fig- ure 15. 1lsb = fs 4096 fs = v ref v output code 011...111 011...110 000...001 111...111 000...010 000...001 000...000 +fs ?lsb v in = ( ain(+) ?in(? ) , input voltage 000...000 0v v ref /2 (v ref /2) +1lsb (v ref /2) ?lsb figure 15. ad7859/ad7859l bipolar transfer characteristic ic1 +3v to +5v 10kw 10kw 10kw v+ v 10kw 50w ad820 ad820-3v v in (? ref /2 to +v ref /2) v ref /2 10? 0.1? 10nf (npo) to ain(+) of ad7854/ad7854l figure 11. analog input buffering input ranges the analog input range for the ad7859/ad7859l is 0 v to v ref in both the unipolar and bipolar ranges. the difference between the unipolar range and the bipolar range is that in the bipolar range the ain(C) should be biased up to at least +v ref /2 and the output coding is 2s complement (see table vi and figures 14 and 15). table vi. analog input connections analog input input connections connection range ain(+) ain(C) diagram 0 v to v ref 1 v in agnd figure 12 v ref /2 2 v in v ref /2 figure 13 notes 1 output code format is straight binary. 2 range is v ref /2 biased about v ref /2. output code format is 2s complement. note that the ain(C) channel on the ad7859/ad7859l can be biased up above agnd in the unipolar mode, or above v ref /2 in bipolar mode if required. the advantage of biasing the lower end of the analog input range away from agnd is that the ana- log input does not have to swing all the way down to agnd. thus, in single supply applications the input amplifier does not have to swing all the way down to agnd. the upper end of the analog input range is shifted up by the same amount. care must be taken so that the bias applied does not shift the upper end of the analog input above the av dd supply. in the case where the reference is the supply, av dd , the ain(C) should be tied to agnd in unipolar mode or to av dd /2 in bipolar mode. track and hold amplifier ain(+) ain(? db0 db15 v in = 0 to v ref ad7859/ad7859l straight binary format figure 12. 0 to v ref unipolar input configuration track and hold amplifier ain(+) ain(? db0 db15 v in = 0 to v ref ad7859/ad7859l 2's complement format v ref /2 figure 13. v ref /2 about v ref /2 bipolar input configuration
ad7859/ad7859l rev. a C17C reference section for specified performance, it is recommended that when using an external reference, this reference should be between 2.3 v and the analog supply av dd . the connections for the reference pins are shown below. if the internal reference is being used, the ref in /ref out pin should be decoupled with a 100 nf capacitor to agnd very close to the ref in /ref out pin. these connections are shown in figure 16. if the internal reference is required for use external to the adc, it should be buffered at the ref in /ref out pin and a 100 nf capacitor should be connected from this pin to agnd. the typical noise performance for the internal reference, with 5 v supplies is 150 nv/ ? hz @ 1 khz and dc noise is 100 m v p-p. ad7859/ad7859l c ref1 c ref2 ref in /ref out 0.1? 0.01? 0.1? av dd dv dd 0.1? 0.1? 10? analog supply +3v to +5v figure 16. relevant connections using internal reference the ref in /ref out pin may be overdriven by connecting it to an external reference. this is possible due to the series resis- tance from the ref in /ref out pin to the internal reference. this external reference can be in the range 2.3 v to av dd . when using av dd as the reference source, the 10 nf capacitor from the ref in /ref out pin to agnd should be as close as possible to the ref in /ref out pin, and also the c ref1 pin should be connected to av dd to keep this pin at the same volt- age as the reference. the connections for this arrangement are shown in figure 17. when using av dd it may be necessary to add a resistor in series with the av dd supply. this has the effect of filtering the noise associated with the av dd supply. note that when using an external reference, the voltage present at the ref in /ref out pin is determined by the external refer- ence source resistance and the series resistance of 150 k w from the ref in /ref out pin to the internal 2.5 v reference. thus, a low source impedance external reference is recommended. ad7859/ad7859l c ref1 c ref2 ref in /ref out 0.1? 0.01? 0.01? av dd dv dd 0.1? 0.1? 10? analog supply +3v to +5v figure 17. relevant connections, av dd as the reference ad7859/ad7859l performance curves figure 18 shows a typical fft plot for the ad7859 at 200 khz sample rate and 10 khz input frequency. frequency ?khz 0 ?0 ?00 0 100 20 40 60 80 ?0 ?0 ?0 av dd = dv dd = 3.3v f sample = 200khz f in = 10khz snr = 72.04db thd = ?8.43db ?20 snr ?db figure 18. fft plot figure 19 shows the snr versus frequency for different sup- plies and different external references. input frequency ?khz s(n+d) ratio ?db 74 73 69 0 100 20 40 60 80 72 71 70 av dd = dv dd with 2.5v reference unless stated otherwise 5.0v supplies, with 5v reference 5.0v supplies 5.0v supplies, l version 3.3v supplies figure 19. snr vs. frequency figure 20 shows the power supply rejection ratio versus fre- quency for the part. the power supply rejection ratio is de- fined as the ratio of the power in adc output at frequency f to the power of a full-scale sine wave. psrr (db) = 10 log (pf/pfs) pf = power at frequency f in adc output, pfs = power of a full- scale sine wave. here a 100 mv peak-to-peak sine wave is coupled onto the av dd supply while the digital supply is left unaltered. both the 3.3 v and 5.0 v supply performances are shown.
ad7859/ad7859l rev. a C18C psrr ?db input frequency ?khz ?8 ?0 ?8 0 100 20 40 60 80 ?2 ?4 ?6 av dd = dv dd = 3.3v/5.0v 100mv pk-pk sinewave on av dd ?0 3.3v 5.0v figure 20. psrr vs. frequency power-down options the ad7859/ad7859l provides flexible power management to allow the user to achieve the best power performance for a given throughput rate. the power management options are selected by programming the power management bits, pmgt1 and pmgt0, in the control register and by use of the sleep pin. table vii summarizes the power-down options that are avail- able and how they can be selected by using either software, hardware or a combination of both. the ad7859/ad7859l can be fully or partially powered down. when fully powered down, all the on-chip circuitry is powered down and i dd is 10 m a typ. if a partial power-down is selected, then all the on-chip circuitry except the reference is powered down and i dd is 400 m a typ. the choice of full or partial power-down does not give any sig- nificant improvement in throughput with a power-down between conversions. this is discussed in the next section power-up times . but a partial power-down does allow the on-chip refer- ence to be used externally even though the rest of the ad7859/ ad7859l circuitry is powered down. it also allows the ad7859/ad7859l to be powered up faster after a long power- down period when using the on-chip reference (see power-up times using on-chip reference ). when using the sleep pin, the power management bits pmgt1 and pmgt0 should be set to zero. bringing the sleep pin logic high ensures normal operation, and the part does not power down at any stage. this may be necessary if the part is being used at high throughput rates when it is not pos- sible to power down between conversions. if the user wishes to power down between conversions at lower throughput rates (i.e., <100 ksps for the ad7859 and <60 ksps for the ad7859l) to achieve better power performances, then the sleep pin should be tied logic low. if the power-down options are to be selected in software only, then the sleep pin should be tied logic high. by setting the power management bits pmgt1 and pmgt0 as shown in table vii, a full power-down, full power-up, full power- down between conversions, and a partial power-down be- tween conversions can be selected. a combination of hardware and software selection can also be used to achieve the desired effect. table vii. power management options pmgt1 pmgt0 sleep bit bit pin comment 0 0 0 full power-down between conversions (hw / sw) 0 0 1 full power-up (hw / sw) 0 1 x full power-down between conversions (sw ) 1 0 x full power-down (sw) 1 1 x partial power-down between conversions (sw) note sw = software selection, hw = hardware selection. power-up times using an external reference when the ad7859/ad7859l are powered up, the parts are powered up from one of two conditions. first, when the power supplies are initially powered up and, secondly, when the parts are powered up from either a hardware or software power-down (see last section). when av dd and dv dd are powered up, the ad7859/ad7859l enters a mode whereby the convst signal initiates a timeout followed by a self-calibration. the total time taken for this time- out and calibration is approximately 70 mssee calibration on power-up in the calibration section of this data sheet. during power-up the functionality of the sleep pin is disabled, i.e., the part will not power down until the end of the calibration if sleep is tied logic low. the power-up calibration mode can be disabled if the user writes to the control register before a convst signal is applied. if the time out and self-calibration are disabled, then the user must take into account the time required by the ad7859/ad7859l to power up before a self- calibration is carried out. this power-up time is the time taken for the ad7859/ad7859l to power up when power is first applied (300 m s typ) or the time it takes the external reference to settle to the 12-bit levelwhichever is the longer. the ad7859/ad7859l powers up from a full hardware or soft- ware power-down in 5 m s typ. this limits the throughput which the part is capable of to 100 ksps for the ad7859 and 60 ksps for the ad7859l when powering down between conversions. figure 21 shows how power-down between conversions is implemented using the convst pin. the user first selects the power-down between conversions option by using the sleep pin and the power management bits, pmgt1 and pmgt0, in the control register. see last section. in this mode the ad7859/ ad7859l automatically enters a full power-down at the end of a conversion, i.e., when busy goes low. the falling edge of the next convst pulse causes the part to power up. assuming the external reference is left powered up, the ad7859/ad7859l should be ready for normal operation 5 m s after this falling edge. the rising edge of convst initiates a conversion so the convst pulse should be at least 5 m s wide. the part automati- cally powers down on completion of the conversion. where the software convert start is used, the part may be powered up in software before a conversion is initiated.
ad7859/ad7859l rev. a C19C power vs. throughput rate the main advantage of a full power-down after a conversion is that it significantly reduces the power consumption of the part at lower throughput rates. when using this mode of operation, the ad7859/ad7859l is only powered up for the duration of the conversion. if the power-up time of the ad7859/ad7859l is taken to be 5 m s and it is assumed that the current during power up is 4.5 ma/1.5 ma typ, then power consumption as a function of throughput can easily be calculated. the ad7859 has a conversion time of 4.6 m s with a 4 mhz external clock and the ad7859l has a conversion time of 9 m s with a 1.8 mhz clock. this means the ad7859/ad7859l consumes 4.5 ma/ 1.5 ma typ for 9.6 m s/14 m s in every conversion cycle if the parts are powered down at the end of a conversion. the two graphs, figure 24 and figure 25, show the power consumption of the ad7859 and ad7859l for v dd = 3 v as a function of through- put. table viii lists the power consumption for various throughput rates. table viii. power consumption vs. throughput power power throughput rate ad7859 ad7859l 1 ksps 130 m w6 5 m w 10 ksps 1.3 mw 650 m w 20 ksps 2.6 mw 1.25 mw 50 ksps 6.48 mw 3.2 mw 1.8mhz oscillator av dd dv dd ain(+) ain(? c ref1 c ref2 sleep db15 db0 convst agnd dgnd clkin ref in /ref out ad7859l analog supply +3v 0.1? 0.1? 10? 0.1? 0.01? conversion start signal 0.1? cal 0v to 2.5v input optional external reference cs rd wr w/b busy dv dd ref192 current, i = 1.5ma typ low power ?/? figure 23. typical low power circuit convst busy 5? 4.6? t convert start conversion on rising edge power up on falling edge power-up time normal operation full power-down power-up time figure 21. using the convst pin to power up the ad7859 for a conversion using the internal (on-chip) reference as in the case of an external reference, the ad7859/ad7859l can power up from one of two conditions, power-up after the supplies are connected or power-up from hardware/software power-down. when using the on-chip reference and powering up when av dd and dv dd are first connected, it is recommended that the power-up calibration mode be disabled as explained above. when using the on-chip reference, the power-up time is effec- tively the time it takes to charge up the external capacitor on the ref in /ref out pin. this time is given by the equation: t up = 9 r c where r ? 150k and c = external capacitor. the recommended value of the external capacitor is 100 nf; this gives a power-up time of approximately 135 ms before a calibration is initiated and normal operation should commence. when c ref is fully charged, the power-up time from a hardware or software power-down reduces to 5 m s. this is because an in- ternal switch opens to provide a high impedance discharge path for the reference capacitor during power-downsee figure 22. an added advantage of the low charge leakage from the refer- ence capacitor during power-down is that even though the refer- ence is being powered down between conversions, the reference capacitor holds the reference voltage to within 0.5 lsbs with throughput rates of 100 samples/second and over with a full power-down between conversions. a high input impedance op amp like the ad707 should be used to buffer this reference capacitor if it is being used externally. note, if the ad7859/ ad7859l is left in its powered-down state for more than 100 ms, the charge on c ref will start to leak away and the power-up time will increase. if this long power-up time is a problem, the user can use a partial power-down for the last con- version so the reference remains powered up. buf on-chip reference to other circuitry switch opens during power-down ref in/out external capacitor figure 22. on-chip reference during power-down
ad7859/ad7859l rev. a C20C power ?mw throughput rate ?ksps 1 0.1 0.01 010 2468 ad7859 full power-down v dd = 3v clkin = 4mhz on-chip reference figure 24. power vs. throughput ad7859 power ?mw throughput rate ?ksps 1 0.1 0.01 020 4 8 12 16 ad7859l full power-down v dd = 3v clkin = 1.8mhz on-chip reference figure 25. power vs. throughput ad7859l power ?mw throughput rate ?ksps 0.01 050 10 20 30 40 0.1 1 10 ad7859 full power-down v dd = 3v clkin = 4mhz on-chip reference figure 26. power vs. throughput ad7859 power ?mw throughput rate ?ksps 0.01 050 10 20 30 40 0.1 1 10 ad7859l full power-down v dd = 3v clkin = 1.8mhz on-chip reference figure 27. power vs. throughput ad7859l
ad7859/ad7859l rev. a C21C calibration section calibration overview the automatic calibration that is performed on power-up ensures that the calibration options covered in this section are not required in a significant number of applications. a calibra- tion does not have to be initiated unless the operating condi- tions change (clkin frequency, analog input mode, reference voltage, temperature, and supply voltages). the ad7859/ ad7859l has a number of calibration features that may be required in some applications, and there are a number of advan- tages in performing these different types of calibration. first, the internal errors in the adc can be reduced significantly to give superior dc performance; and second, system offset and gain er- rors can be removed. this allows the user to remove reference errors (whether it be internal or external reference) and to make use of the full dynamic range of the ad7859/ad7859l by ad- justing the analog input range of the part for a specific system. there are two main calibration modes on the ad7859/ad7859l, self-calibration and system calibration. there are various op- tions in both self-calibration and system calibration as outlined previously in table iv. all the calibration functions are initi- ated by writing to the control register and setting the stcal bit to 1. the duration of each of the different types of calibration is given in table ix for the ad7859 with a 4 mhz master clock. these calibration times are master clock dependent. therefore the calibration times for the ad7859l (clkin = 1.8 mhz) are larger than those quoted in table ix. table ix. calibration times (ad7859 with 4 mhz clkin) type of self-calibration or system calibration time full 31.25 ms gain + offset 6.94 ms offset 3.47 ms gain 3.47 ms calibration on power-on the calibration on power-on is initiated by the first convst pulse after the av dd and dv dd power on. from the con vs t pulse the part internally sets a 32/72 ms (4 mhz/1.8 mhz clkin) timeout. this time is large enough to ensure that the internal reference has settled before the calibration is performed. however, if an external reference is being used, this reference must have stabilized before the automatic calibration is initiated. this first convst pulse also triggers the busy signal high, and once the 32/72 ms has elapsed, the busy signal goes low. at this point the next convst pulse that is applied initiates the automatic full self-calibration. this convst pulse again triggers the busy signal high, and after 32/72 ms (4 mhz/ 1.8 mhz clkin), the calibration is completed and the busy signal goes low. this timing arrangement is shown in figure 28. the times in figure 28 assume a 4 mhz/1.8 mhz clkin signal. av dd = dv dd convst busy power-on 32/72ms 32/72ms timeout period automatic calibration duration conversion is initiated on this edge figure 28. timing arrangement for autocalibration on power-on the convst signal is gated with the busy internally so that as soon as the timeout is initiated by the first convst pulse all subsequent convst pulses are ignored until the busy signal goes low, 32/72 ms later. the convst pulse that follows after the busy signal goes low initiates a full self-calibration. this takes a further 32/72 ms. after calibration, the part is accurate to the 12-bit level and the specifications quoted on the data sheet apply; all subsequent convst pulses initiate conver- sions. there is no need to perform another calibration unless the operating conditions change or unless a system calibration is required. this autocalibration at power-on is disabled if the user writes to the control register before the autocalibration is initiated. if the control register write operation occurs during the first 32/72 ms timeout period, then the busy signal stays high for the 32/72 ms and the convst pulse that follows the busy going low does not initiate a full self-calibration. it initiates a conversion and all subsequent convst pulses initiate conversions as well. if the control register write operation occurs when the automatic full self-calibration is in progress, then the calibration is not be aborted; the busy signal remains high until the automatic full self-calibration is complete. self-calibration description there are four different calibration options within the self- calibration mode. there is a full self-calibration where the dac, internal offset, and internal gain errors are removed. there is the (gain + offset) self-calibration which removes the internal gain error and then the internal offset errors. the inter- nal dac is not calibrated here. finally, there are the self-offset and self-gain calibrations which remove the internal offset errors and the internal gain errors respectively. the internal capacitor dac is calibrated by trimming each of the capacitors in the dac. it is the ratio of these capacitors to each other that is critical, and so the calibration algorithm en- sures that this ratio is at a specific value by the end of the cali- bration routine. for the offset and gain there are two separate capacitors, one of which is trimmed during offset calibration and one of which is trimmed during gain calibration. in bipolar mode the midscale error is adjusted by an offset cali- bration and the positive full-scale error is adjusted by the gain calibration. in unipolar mode the zero-scale error is adjusted by the offset calibration and the positive full-scale error is ad- justed by the gain calibration.
ad7859/ad7859l rev. a C22C self-calibration timing figure 29 shows the timing for a software full self-calibration. here the busy line stays high for the full length of the self- calibration. a self-calibration is initiated by writing to the control register and setting the stcal bit to 1. the busy line goes high at the end of the write to the control register, and busy goes low when the full self-calibration is complete after a time t cal as show in figure 29. t 19 data latched into control register hi-z hi-z data valid cs wr data busy t cal figure 29. timing diagram for full self-calibration for the self-(gain + offset), self-offset and self-gain calibrations, the busy line is triggered high at the end of the write to the control register and stays high for the full duration of the self- calibration. the length of time for which busy is high depends on the type of self-calibration that is initiated. typical values are given in table ix. the timing diagram for the other self-calibration options is similar to that outlined in figure 29. system calibration description system calibration allows the user to remove system errors ex- ternal to the ad7859/ad7859l, as well as remove the errors of the ad7859/ad7859l itself. the maximum calibration range for the system offset errors is 5% of v ref and for the system gain errors, it is 2.5% of v ref . if the system offset or system gain errors are outside these ranges, the system calibration algo- rithm reduces the errors as much as the trim range allows. figures 30 through 32 illustrate why a specific type of system calibration might be used. figure 30 shows a system offset cali- bration (assuming a positive offset) where the analog input range has been shifted upwards by the system offset after the system offset calibration is completed. a negative offset may also be removed by a system offset calibration. max system full scale is 2.5% from v ref max system offset is 5% of v ref analog input range v ref + sys offset v ref ?1lsb system offset calibration sys offset agnd analog input range v ref ?1lsb sys offset agnd max system offset is 5% of v ref figure 30. system offset calibration figure 31 shows a system gain calibration (assuming a system full scale greater than the reference voltage) where the analog input range has been increased after the system gain calibration is completed. a system full-scale voltage less than the reference voltage may also be accounted for a by a system gain calibration. analog input range max system full scale is 2.5% from v ref system gain calibration analog input range v ref ?1lsb agnd sys full s. max system full scale is 2.5% from v ref v ref ?1lsb sys full s. agnd figure 31. system gain calibration finally in figure 32 both the system offset error and gain error are removed by the system offset followed by a system gain cali- bration. first the analog input range is shifted upwards by the positive system offset and then the analog input range is adjusted at the top end to account for the system full scale. max system full scale is 2.5% from v ref analog input range v ref + sys offset sys offset agnd analog input range v ref ?1lsb sys offset agnd max system offset is 5% of v ref max system offset is 5% of v ref system gain calibration system offset calibration followed by v ref ?1lsb sys f.s. sys f.s. max system full scale is 2.5% from v ref figure 32. system (gain + offset) calibration
ad7859/ad7859l rev. a C23C system gain and offset interaction the architecture of the ad7859/ad7859l leads to an interac- tion between the system offset and gain errors when a system calibration is performed. therefore, it is recommended to per- form the cycle of a system offset calibration followed by a sys- tem gain calibration twice. when a system offset calibration is performed, the system offset error is reduced to zero. if this is followed by a system gain calibration, then the system gain error is now zero, but the system offset error is no longer zero. a sec- ond sequence of system offset error calibration followed by a system gain calibration is necessary to reduce system offset error to below the 12-bit level. the advantage of doing separate system offset and system gain calibrations is that the user has more control over when the analog inputs need to be at the required levels, and the convst signal does not have to be used. alternatively, a system (gain + offset) calibration can be per- formed. at the end of one system (gain + offset) calibration, the system offset error is zero, while the system gain error is reduced from its initial value. three system (gain + offset) calibrations are required to reduce the system gain error to below the 12-bit error level. there is never any need to perform more than three system (gain + offset) calibrations. in bipolar mode the midscale error is adjusted for an offset cali- bration and the positive full-scale error is adjusted for the gain calibration; in unipolar mode the zero-scale error is adjusted for an offset calibration and the positive full-scale error is adjusted for a gain calibration. system calibration timing the timing diagram in figure 33 is for a software full system calibration. it may be easier in some applications to perform separate gain and offset calibrations so that the convst bit in the control register does not have to be programmed in the middle of the system calibration sequence. once the write to the control register setting the bits for a full system calibration is completed, calibration of the internal dac is initiated and the busy line goes high. the full-scale system voltage should be applied to the analog input pins, ain(+) and ain(C) at the start of calibration. the busy line goes low once the dac and sys- tem gain calibration are complete. next the system offset volt- age should be applied across the ain(+) and ain(C) pins for a minimum setup time (t setup ) of 100 ns before the rising edge of cs . this second write to the control register sets the convst bit to 1 and at the end of this write operation the busy signal is triggered high (note that a convst pulse can be applied in- stead of this second write to the control register). the busy signal is low after a time t cal2 when the system offset calibration section is complete. the full system calibration is now complete. the timing for a system (gain + offset) calibration is very similar to that of figure 33, the only difference being that the time t cal1 is replaced by a shorter time of the order of t cal2 as the in- ternal dac is not calibrated. the busy signal signifies when the gain calibration is finished and when the part is ready for the offset calibration. t 19 data latched into control register hi-z hi-z hi-z t 19 t setup data valid t cal1 t cal2 v offset convst bit set to 1 in control register cs wr data busy ain data valid v system full scale figure 33. timing diagram for full system calibration the timing diagram for a system offset or system gain calibra- tion is shown in figure 34. here again a write to the control reg- ister initiates the calibration sequence. at the end of the control register write operation the busy line goes high and it stays high until the calibration sequence is finished. the analog input should be set at the correct level for a minimum setup time (t setup ) of 100 ns before the cs rising edge and stay at the cor- rect level until the busy signal goes low. t 19 hi-z hi-z data latched into control register t setup busy ain cs wr data data valid t cal2 v system full scale or v offset figure 34. timing diagram for system gain or system offset calibration
ad7859/ad7859l rev. a C24C data valid data valid t 16 t 15 t 17 t 14 t 13 t convert t 1 t 18 t 5 t 6 t 7 t 8 t 9 * w/b pin logic high busy cs wr db0 ?db15 convst rd internal data latch old data new data figure 35. read and write cycle timing diagram for 16-bit transfers figure 35 shows the read cycle timing diagram for 16-bit trans- fers for the ad7859. when operated in word mode, the hben input does not exist, and only the first read operation is required to access data from the ad7859. valid data, in this case, is pro- vided on db0Cdb15. when operated in byte mode, the two read cycles shown in figure 36 are required to access the full data word from the ad7859. note that in byte mode, the order of successive read operations is important when reading the cali- bration registers. this is because the register file address pointer is incremented on a high byte read as explained in the calibra- tion register section of this data sheet. in this case the order of the read should always be low byteChigh byte. in figure 36, the first read places the lower 8 bits of the full data word on db0Cdb7 and the second read places the upper 8 bits of the data word on db0Cdb7. the cs and rd signals are gated internally and level-triggered active low. in either word or byte mode, cs and rd may be tied together as the timing specification for t 5 and t 6 is 0 ns min. the data is output a time t 8 after both cs and rd go low. the rd rising should be used to latch data by the user and after a time t 9 the data lines will become three-stated. parallel interface the ad7859 provides a flexible, high speed, parallel interface. this interface is capable of operating in either word (with the w/ b pin tied high) or byte (with w/ b tied low) mode. a detailed description of the different interface arrangements follows. reading with the w/ b pin at a logic high, the ad7859 interface operates in word mode. in this case, a single read operation from the device accesses the word on pins db0 to db15 (for a data read, the 12-bit conversion result appears on db0Cdb11). db0 is the lsb of the word. the db8/hben pin assumes its db8 function. with the w/ b pin at a logic low, the ad7859 interface operates in byte mode. in this case, the db8/hben pin as- sumes its hben function. data to be accessed from the ad7859 must be accessed in two read operations with 8 bits of data provided by the ad7859 on db0Cdb7 for each of the read operations. the hben pin determines whether the read operation accesses the high byte or low byte of the 16-bit word. for a low byte read, db0 provides the lsb of the 16-bit word. for a high byte read db0 provides data bit 8 of the 16-bit word with db7 providing the msb of the 16-bit word. t 3 t 4 t 3 t 4 t 5 t 10 t 6 t 7 t 8 t 9 low byte high byte * w/b pin logic low hben cs rd db0 ?db7 figure 36. read cycle timing for byte mode operation
ad7859/ad7859l rev. a C25C t 11 t 12 t 11 t 12 t 13 t 14 t 15 t 16 t 17 low byte high byte * w/b pin logic low hben cs wr db0 ?db7 figure 37. write cycle timing for byte mode operation writing with w/ b at a logic high, a single write operation transfers the full data word to the ad7859. the db8/hben pin assumes its db8 function. data to be written to the ad7859 should be pro- vided on the db0Cdb15 inputs with db0 the lsb of the data word. with w/ b at a logic low, the ad7859 requires two write operations to transfer a full 16-bit word. db8/hben assumes its hben function. data to be written to the ad7859 should be provided on the db0Cdb7 inputs. hben determines whether the byte which is to be written is high byte or low byte data. the low byte of the data word should be written first with db0 the lsb of the full data word. for the high byte write, hben should be high and the data on the db0 input should be data bit 8 of the 16-bit word with the data on db7 the msb of the 16-bit word. figure 35 shows the write cycle timing diagram for the ad7859. when operated in word mode, the hben input does not exist and only the first write operation is required to write data to the ad7859. data should be provided on db0Cdb15. when oper- ated in byte mode, the two write cycles shown in figure 37 are required to write the full data word to the ad7859. in figure 37, the first write transfers the lower 8 bits of the full data from db0Cdb7 and the second write transfers the upper 8 bits of the data word from db0-db7. the cs and wr signals are gated internally. cs and wr may be tied together as the timing specification for t 13 and t 14 is 0 ns min. the data is latched on the rising edge of wr . the data needs to be set up a time t 16 before the wr rising edge and held for a time t 17 after the wr rising edge. resetting the parallel interface in the case where incorrect data is inadvertently written to the ad7859, there is a possibility that the test register contents may have been altered. if there is a suspicion that this may have happened and the part is not operating as expected, a 16-bit word 0000 0000 0000 0010 should be written to the ad7859 to restore the test register contents to the default value. microprocessor interfacing interfacing the ad7859/ad7859l to a 16-bit data bus the parallel port on the ad7859 allows the device to be inter- faced to microprocessors or dsp processors as a memory- mapped or i/o-mapped device. the cs and rd inputs are common to all memory peripheral interfacing. typical inter- faces to different processors are shown in figures 38 to 42. in all the interfaces shown, an external timer controls the convst input of the ad7859/ad7859l, the busy output interrupts the host dsp and the w/ b input is logic high. ad7859/ad7859l to adsp-21xx figure 38 shows the ad7859/ad7859l interfaced to the adsp-21xx series of dsps as a memory mapped device. a single wait state may be necessary to interface the ad7859/ ad7859l to the adsp-21xx depending on the clock speed of the dsp. this wait state can be programmed via the data memory waitstate control register of the adsp-21xx (please see adsp-2100 family users manual for details). the following instruction reads data from the ad7859/ad7859l: mr = dm(adc) where adc is the address of the ad7859/ad7859l. adsp-21xx* cs db15?b0 ad7859/ ad7859l* *additional pins omitted for clarity d23?8 addr decode dms data bus wr rd address bus en wr rd irq2 a13?0 busy figure 38. ad7859/ad7859l to adsp-21xx parallel interface ad7859/ad7859l to tms32020, tms320c25 and tms320c5x parallel interfaces between the ad7859/ad7859l and the tms32020, tms320c25 and tms320c5x family of dsps are shown in figure 39. the memory mapped address chosen for the ad7859/ad7859l should be chosen to fall in the i/o memory space of the dsps. tms32020/ tms320c25/ tms320c50* cs db15?b0 ad7859/ ad7859l* *additional pins omitted for clarity d23?0 addr decode data bus wr rd address bus strb intx a15?0 r/w en is msc ready tms320c25 only busy figure 39. ad7859/ad7859l to tms32020/c25/c5x parallel interface
ad7859/ad7859l rev. a C26C the parallel interface on the ad7859/ad7859l is fast enough to interface to the tms32020 with no extra wait states. if high speed glue logic such as 74as devices are used to drive the wr and rd lines when interfacing to the tms320c25, then again no wait states are necessary. however, if slower logic is used, data accesses may be slowed sufficiently when reading from and writing to the part to require the insertion of one wait state. in such a case, this wait state can be generated using the single or gate to combine the cs and msc signals to drive the ready line of the tms320c25, as shown in figure 39. extra wait states will be necessary when using the tms320c5x at their fastest clock speeds. wait states can be programmed via the iowsr and cwsr registers (please see tms320c5x user guide for details). data is read from the adc using the following instruction: in d,adc where d is the memory location where the data is to be stored and adc is the i/o address of the ad7859/ad7859l. ad7859/ad7859l to tms320c30 figure 40 shows a parallel interface between the ad7859/ ad7859l and the tms320c3x family of dsps. the ad7859/ ad7859l is interfaced to the expansion bus of the tms320c3x. a single wait state is required in this interface. this can be pro- grammed using the wtcnt bits of the expansion bus control register (see tms320c3x users guide for details). data from the ad7859/ad7859l can be read using the following instruction: ldi *arn,rx where arn is an auxiliary register containing the lower 16 bits of the address of the ad7859/ad7859l in the tms320c3x memory space and rx is the register into which the adc data is loaded. tms320c30* cs db15?b0 ad7859/ ad7859l* *additional pins omitted for clarity xd23?d0 addr decode expansion data bus wr rd expansion address bus iostrb intx xa12?a0 xr/w busy figure 40. ad7859/ad7859l to tms320c30 parallel interface ad7859/ad7859l to dsp5600x figure 41 shows a parallel interface between the ad7859/ ad7859l and the dsp5600x series of dsps. the ad7859/ ad7859l should be mapped into the top 64 locations of y data memory. if extra wait states are needed in this interface, they can be programmed using the port a bus control register (please see dsp5600x users manual for details). data can be read from the ad7859/ad7859l using the following instruction: moveo y:adc,x0 where adc is the address in the dsp5600x address space which the ad7859/ad7859l has been mapped to. dsp56000/ dsp56002* cs db15?b0 ad7859/ ad7859l* *additional pins omitted for clarity d23?0 addr decode ds data bus wr rd address bus wr rd irq a15?0 x/y busy figure 41. ad7859/ad7859l to dsp5600x parallel interface interfacing the ad7859/ad7859l to an 8-bit data bus ad7859/ad7859l to 8051 this mode of operation allows the ad7859/ad7859l to be in- terfaced directly to microcontrollors with an 8-bit data bus. the ad7859/ad7859l is placed in byte mode by placing a logic low signal on the w/ b pin. figure 42 shows a parallel interface between the ad7859/ ad7859l and the 8051 microcontroller. here the w/ b pin is tied logic low and the db8/hben pin connected to line 1 of port 2. port 0 serves as a multiplexed address/data bus to the ad7859/ad7859l. alternatively if the 8051 is not using exter- nal memory or other memory mapped peripheral devices, line 2 of port 2 (or any other line) could be used as the cs signal. 8051* addr decode cs db7?b0 ad7859/ ad7859l* *additional pins omitted for clarity wr rd wr rd int0 p0 busy latch ale p2.1 db8/hben w/b dgnd figure 42. ad7859/ad7859l to 8051 parallel interface application hints grounding and layout the analog and digital supplies of the ad7859/ad7859l are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. the part has very good immunity to noise on the power supplies as can be seen by the psrr versus frequency graph. however, care should still be taken with regard to grounding and layout. the printed circuit board on which the ad7859/ad7859l is mounted should be designed such that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be eas- ily separated. a minimum etch technique is generally best for ground planes as it gives the best shielding. digital and analog ground planes should only be joined in one place. if the ad7859/ad7859l is the only device requiring an agnd to
ad7859/ad7859l rev. a C27C dgnd connection, then the ground planes should be con- nected at the agnd and dgnd pins of the ad7859/ ad7859l. if the ad7859/ad7859l is in a system where mul- tiple devices require agnd to dgnd connections, the con- nection should still be made at one point only, a star ground point which should be established as close as possible to the ad7859/ad7859l. avoid running digital lines under the device as these couple noise onto the die. the analog ground plane should be allowed to run under the ad7859/ad7859l to avoid noise coupling. the power supply lines to the ad7859/ad7859l should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals like clocks and the data inputs should be shielded with digital ground to avoid radiating noise to other sections of the board and clock signals should never be run near the analog inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is by far the best but is not al- ways possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. good decoupling is also important. all analog supplies should be decoupled with a 10 m f tantalum capacitor in parallel with 0.1 m f disc ceramic capacitor to agnd. all digital supplies should have a 0.1 m f disc ceramic capacitor to dgnd. to achieve the best performance from these decoupling compo- nents, they must be placed as close as possible to the device, ideally right up against the device. in systems where a common supply voltage is used to drive both the av dd and dv dd of the ad7859/ad7859l, it is recommended that the systems av dd supply is used. in this case an optional 10 w resistor between the av dd pin and dv dd pin can help to filter noise from digital circuitry. this supply should have the recommended analog supply decoupling capacitors between the av dd pin of the ad7859/ad7859l and agnd and the recommended digital supply decoupling capacitor between the dv dd pin of the ad7859/ad7859l and dgnd. evaluating the ad7859/ad7859l performance the recommended layout for the ad7859/ad7859l is outlined in the evaluation board for the ad7859/ad7859l. the evalua- tion board package includes a fully assembled and tested evalua- tion board, documentation, and software for controlling the board from the pc via the eval-control board. the eval-control board can be used in conjunction with the ad7859/ad7859l evaluation board, as well as many other analog devices evaluation boards ending in the cb designator, to demonstrate/evaluate the ac and dc performance of the ad7859/ad7859l. the software allows the user to perform ac (fast fourier trans- form) and dc (histogram of codes) tests on the ad7859/ ad7859l. it also gives full access to all the ad7859/ad7859l on-chip registers allowing for various calibration and power- down options to be programmed. ad785x family all parts are 12 bits, 200 ksps, 3.0 v to 5.5 v. ad7853 C single-channel serial ad7854 C single-channel parallel ad7858 C eight-channel serial ad7859 C eight-channel parallel
printed in u.s.a. c2109C7C1/96 C28C outline dimensions dimensions shown in inches and (mm). 44-lead plcc (p-44a) 0.032 (0.81) 0.026 (0.66) 0.021 (0.53) 0.013 (0.33) 0.056 (1.42) 0.042 (1.07) 0.025 (0.63) 0.015 (0.38) 0.180 (4.57) 0.165 (4.19) 0.63 (16.00) 0.59 (14.99) 0.110 (2.79) 0.085 (2.16) 0.040 (1.01) 0.025 (0.64) 0.050 (1.27) bsc 0.656 (16.66) 0.650 (16.51) sq 0.695 (17.65) 0.685 (17.40) sq 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 40 6 top view 39 29 18 17 pin 1 identifier 7 28 0.020 (0.50) r 44-pin pqfp (s-44) 1 44 34 33 23 22 12 11 top view pin 1 0.557 (14.15) 0.537 (13.65) 0.397 (10.1) 0.390 (9.9) 0.016 (0.4) 0.012 (0.3) 0.033 (0.85) 0.029 (0.75) 0.037 (0.95) 0.026 (0.65) 0.398 (10.1) 0.390 (9.9) 0.083 (2.1) 0.077 (1.95) 0.040 (1.02) 0.032 (0.82) 0.040 (1.02) 0.032 (0.82) 0.096 (2.45) max 8 0 page index topic page features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 product highlights . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . 5 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin function description . . . . . . . . . . . . . . . . . . . . . . 7 ad7859/ad7859l on-chip registers . . . . . . . . . . . . . . . 8 addressing the on-chip registers . . . . . . . . . . . . . . . . . . . . . . 8 writing/reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 calibration registers . . . . . . . . . . . . . . . . . . . . . . . . . 12 addressing the calibration registers . . . . . . . . . . . . . . . . . . . 12 writing to/reading from the calibration registers . . . . . . . . 12 adjusting the offset calibration register . . . . . . . . . . . . . . . . 13 adjusting the gain calibration registers . . . . . . . . . . . . . . . . 13 circuit information . . . . . . . . . . . . . . . . . . . . . . . . . . 14 converter details . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 typical connection diagram . . . . . . . . . . . . . . . . . 14 analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 acquisition time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 dc/ac applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 input ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 transfer functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 reference section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ad7859/ad7859l performance curves . . . . . . . . . . 17 power-down options . . . . . . . . . . . . . . . . . . . . . . . . . . 18 power-up times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 power vs. throughput rate . . . . . . . . . . . . . . . . . . 19 calibration section . . . . . . . . . . . . . . . . . . . . . . . . . . 21 calibration overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 calibration on power-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 self-calibration description . . . . . . . . . . . . . . . . . . . . . . . . . 21 self-calibration timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 system calibration description . . . . . . . . . . . . . . . . . . . . . . . 22 system gain and offset interaction . . . . . . . . . . . . . . . . . . . . 23 system calibration timing . . . . . . . . . . . . . . . . . . . . . . . . . . 23 parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 microprocessor interfacing . . . . . . . . . . . . . . . . 25 applications hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 grounding and layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 evaluating the ad7859/ad7859l performance . . . . . . . . . . 27 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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